1. Field of the Invention
The present invention relates to a CMOS image sensor and a method for manufacturing the same, and more particularly, to a CMOS image sensor in which an n-type impurity region is formed between a photodiode and a transfer transistor for decreasing a dark current and dead-zone, and a method for manufacturing the same.
2. Discussion of the Related Art
Generally, image sensors are semiconductor devices for converting an optical image into an electric signal. The image sensors are basically classified into charge coupled devices (CCDs) or complementary metal oxide silicon (CMOS) image sensors.
The charge coupled device (CCD) includes a plurality of photodiodes, which are arranged in a matrix, each photodiode converting an optical signal into an electric signal. In the matrix of the photodiodes, a plurality of vertical charge coupled devices (VCCDs) are provided between the respective vertically arranged neighboring photodiodes to transmit electric charges, generated by the respective photodiodes, in a vertical direction, and a plurality of horizontal charge coupled devices (HCCDs) are provided to transmit the electric charges, transmitted by the respective vertical charge coupled devices, in a horizontal direction. Also, a sense amplifier is provided to sense the horizontally transmitted electric charges, and consequently, to output electric signals.
Disadvantages of the charge coupled device (CCD) include a complicated driving method, high electric power consumption, and a complicated manufacturing process requiring a multi-step photo process. In the case of the charge coupled device (CCD), it is also difficult to integrate a control circuit, signal processing circuit, analog/digital conversion circuit (A/D converter), and other components into a charge coupled device chip. This makes it impossible to achieve compact-sized products.
Recently, the complementary metal oxide silicon (CMOS) image sensor has been proposed to solve the problems associated with the charge coupled device (CCD). The CMOS image sensor is a device employing CMOS technology, which uses a control circuit and signal processing circuit as peripheral circuits, such that a number of MOS transistors, each associated with a unit pixel, are formed on a semiconductor substrate, whereby outputs of the respective unit pixels are sequentially detected by the MOS transistors by a switching method. That is, in the CMOS image sensor, a photodiode and MOS transistor are formed in a unit pixel to sequentially detect electric signals of the respective unit pixels by a switching method, thereby achieving an image.
As a result of employing CMOS manufacturing technology, the CMOS image sensor can have several advantages, for example, low electric power consumption, and a simplified manufacturing process based on a reduced number of photo process steps. Also, the CMOS image sensor enables a control circuit, signal processing circuit, analog/digital conversion circuit, and other components to be integrated into a CMOS image sensor chip, and therefore, can easily achieve a compact product size. For this reason, the CMOS image sensor is widely applied in various fields, such as for example, digital still cameras and digital video cameras.
Meanwhile, the CMOS image sensors may be classified into 3T-type, 4T-type, or 5T-type CMOS image sensors in accordance with the number of transistors. The 3T-type CMOS image sensor has one photodiode and three transistors, and the 4T-type CMOS image sensor has one photodiode and four transistors.
FIG. 1 is a diagram illustrating the layout of a unit pixel provided in a conventional 4T-type CMOS image sensor, and FIG. 2 is an equivalent circuit diagram illustrating the unit pixel of the conventional 4T-CMOS image sensor of FIG. 1.
As shown in FIGS. 1 and 2, the unit pixel of the conventional 4T-type CMOS image sensor includes an active region 10 defined therein, such that one photodiode 20 is formed in a wide portion of the active region 10, and gate electrodes 110, 120, 130, and 140 of four transistors are formed to overlap with the remaining active region 10. Specifically, a transfer transistor Tx is formed by the gate electrode 110, a reset transistor Rx is formed by the gate electrode 120, a drive transistor Dx is formed by the gate electrode 130, and a select transistor Sx is formed by the gate electrode 140. Here, impurity ions are injected into the active region 10 of the respective transistors, except for portions below the gate electrodes 110, 120, 130, and 140, such that source/drain regions of the respective transistors are formed. Accordingly, a power supply voltage Vdd is applied to the source/drain region between the reset transistor Rx and the drive transistor Dx, and a power supply voltage Vss is applied to the source/drain region at a side of the select transistor Sx.
Hereinafter, a method for manufacturing the conventional CMOS image sensor having the above described configuration will be described.
FIGS. 3A to 3E are sectional views illustrating the sequential processes of a conventional CMOS image sensor manufacturing method, taken along line I-I of FIG. 1.
Referring to FIG. 3A, a low-density p-type epitaxial layer 2 is formed on a p-type semiconductor substrate 1. Subsequently, the epitaxial layer 2 is subjected to exposure and development processes using a mask, which defines an active region and a device isolation region, such that the epitaxial layer 2 of the device isolation region is etched to a predetermined depth to form a trench. Then, an O3 TEOS film is formed on the substrate to fill the trench, and is patterned by use of a chemical mechanical polishing (CMP) process to remain only in the trench region. In this way, a device isolation film 3 is formed in the device isolation region.
A gate insulation film and a conductive layer are then formed on an entire surface of the substrate in this sequence and are selectively removed to form a gate insulation film 4 and a gate electrode 5.
Referring to FIG. 3B, a photoresist film is deposited on the entire surface of the substrate and subjected to exposure and development processes, such that a photoresist film pattern 6 is formed to expose a photodiode region. Specifically, the photoresist film pattern 6 is configured such that it exposes a part of the gate electrode 5 while covering a part of the active region adjacent to the device isolation film 3. Then, n-type impurity ions are injected into the epitaxial layer 2 of the photodiode region via a high-energy ion injection process to form a photodiode n-type impurity region 7. After the formation of the photodiode n-type impurity region 7, the photoresist film pattern 6 is removed.
When the photodiode n-type impurity region 7 is formed by injecting the n-type impurity ions via the high-energy ion injection process, the n-type impurity ions may be doped into a channel region below the gate electrode 5 by passing through the gate electrode 5. Here, it should be noted that the transfer transistor should be manufactured to have a low threshold voltage for a fast transfer of electric charges. However, since the n-type impurity ions are doped into the channel region below the gate electrode 5, a threshold voltage value Vth of the transfer transistor is lowered below a target value, thereby resulting in an increase in off leakage current.
In succession, an insulation film is deposited on the entire surface of the substrate and subjected to an etch-back process to form a sidewall insulation film on sidewalls of the gate electrode 5. Then, after a photoresist layer pattern is formed to expose the photodiode region, p-type impurity ions are injected into a surface of the photodiode n-type impurity region 7 to form a photodiode p-type impurity region. However, when the etch-back process is performed to form a spacer on the sidewalls of the gate electrode 5, the surface of the photodiode region may exhibit ion damage resulting from increased crystal defects. Consequently, the resulting CMOS image sensor may suffer from an increase of dark-current. Accordingly, to solve this problem, a spacer block mask has been used instead of forming the spacer.
Specifically, referring to FIG. 3C, after the photoresist film pattern 9 is formed to expose the photodiode region without forming the spacer, p-type impurity ions are injected into the surface of the photodiode n-type impurity region 7 to form the photodiode p-type impurity region 10.
Subsequently, referring to FIG. 3D, an insulation film 11 and a photoresist film are deposited on the entire surface of the semiconductor substrate in this sequence and subjected to exposure and development processes, such that a photoresist film pattern 12 is formed to cover the photodiode region. After that, referring to FIG. 3E, the insulation film 11 is selectively removed by use of the photoresist film pattern 12 as a mask to form a spacer block mask 11a. 
The spacer block mask forming process as described with reference to FIGS. 3C to 3E is advantageous to minimize the generation of ion damage on the surface of the photodiode region. However, due to the fact that the p-type impurity ions are injected into the surface of the photodiode n-type impurity region 7 prior to forming the spacer block mask, the p-type impurity ions may be heavily doped with an increased density in a source region of the transfer transistor (See FIGS. 1 and 2). This increases a potential barrier in the transfer of electric charges generated from the photodiode, resulting in an increase of dead zone, which exposes the sensor to an excessive quantity of light and thus, prevents the generation of signals for a certain amount of time. Further, when the p-type impurity ions are injected, they may have an effect on a region below the gate electrode of the transfer transistor, thereby deteriorating the channeling of the transfer transistor.